1. Field
The disclosed embodiments relate generally to pseudo-dual port memories.
2. Background
Dual port memories typically have two ports and an array of memory cells. The memory array can be simultaneously accessed from both of the ports provided that the memory cells being accessed from one port are not the same memory cells that are being accessed from the other port. A common type of memory cell used in such dual port memories involves eight field effect transistors (FETs). Four of the transistors are interconnected to form two cross-coupled inverters. A first data node D of the memory cell is the node at the output lead of a first of the inverters and the input lead of the second of the inverters. A second data node DN of the memory cell is the node at the output lead of the second of the inverters and the input lead of the first of the inverters. There are two access transistors coupled to the first data node D. The first access transistor is provided so that a first bit line B1 can selectively be coupled to the first data node D. The second access transistor is provided so that a second bit line B2 can selectively be coupled to the first data node D. Similarly, there are two access transistors coupled to the second data node DN. The first access transistor is provided so that a first bit line bar B1N can be coupled to the second node DN. The second access transistor is provided so that a second bit line bar B2N can be coupled to the second node DN. The first bit line B1 and first bit line bar B1N constitute a bit line pair and a for coupling an addressed memory cell to a first of the two ports of the dual port memory. The second bit line B2 and second bit line bar B2N constitute a bit line pair and are for coupling an addressed memory cell to a second of the two ports of the dual port memory.
The memory cells in a single port memory typically only include six transistors. As in the case of the eight-transistor cell, four of the transistors form a cross-coupled inverter structure. Rather than there being two pairs of access transistors as in the eight transistor cell, however, the six transistor cell has only one pair of access transistors. A first access transistor is provided for selectively coupling the first data node D of the cross-coupled inverters to a bit line B. A second access transistor is provided for coupling a second data node DN of the cross-coupled inverters to a bit line bar BN. The six-transistor memory cell typically consumes only about half as much integrated circuit area than the eight-transistor cell when the two types of memory cells are fabricated using the same process.
In order to take advantage of the smaller size of the six-transistor memory cell, a memory device called a pseudo-dual port memory is often used. In one example, a pseudo-dual port memory has a single memory array where each memory cell of the array is a six-transistor memory cell that can be selectively coupled to a single pair of bit lines (for example, bit line B and bit line bar BN). The memory array operates as a single port memory in that only one memory access is performed at one time.
The pseudo-dual port memory, however, mimics a dual port memory in that it has two ports. Within a single cycle of a clock signal supplied to the pseudo dual port memory, it appears that a first access of the memory array is performed from one port and that a second access of the memory array is performed from the other port. In reality, though, two accesses of the memory array are performed in rapid succession. If, for example, a read operation is to be performed from the first port of the pseudo-dual port memory and a write operation is to be performed from the second port of the pseudo-dual port memory, then data from addressed memory cells are output onto the data terminals of the first port at a first time where the address of the addressed memory cells is provided on address terminals of the first port. After the read operation, then a write operation is performed where data on the data terminals of the second port is written into addressed memory cells where the address of the addressed memory cells is provided on the address terminals of the second port. The two accesses occur in rapid succession such that from outside the pseudo-dual port memory, the pseudo-dual port memory appears to allow two accesses of the memory array at the same time (i.e., during a single cycle of the externally supplied clock signal).
Within the pseudo-dual port memory, a structure sometimes known as a Time Delayed Multiplexer (TDM) works to control the two accesses of the single memory array. The TDM uses the rising edge of the clock signal to initiate the first memory access. The TDM uses the falling edge of the clock signal to initiate the second memory access.
Where there are two memory accesses to be performed on a single memory array in a pseudo-dual port memory, the inventor has recognized that the amount of time required to perform the first access may sometimes not be equal to the amount of time required to perform the second access. For example, in some memory array configurations, the amount of time required to perform a first memory read operation is smaller than the amount of time required to perform a second memory write operation. Using a conventional TDM approach slows overall memory access times because the relative amounts of time available for the two operations is determined by the time when the rising edge of the clock cycle occurs and the time when the falling edge of the clock cycle occurs. If, for example, the clock signal is low for as long as it is high in a clock cycle (i.e., the clock signal has a 50/50 duty cycle), then the same amount of time must be allowed for performing both the faster read operation and the slower write operation. The result is an amount of wasted time that starts after the read operation has been completed and ends upon the falling edge of the clock signal.
Not only does the conventional TDM approach sometimes slow overall memory access times in situations where the relative amounts of time required to perform the two memory access does not match the duty cycle of the clock signal, but the conventional TDM approach also can cause overall memory access times to be slower than they otherwise would have to be due to the use of the falling edge of the clock signal to initiate operations. There may be jitter in the duty cycle of the clock signal such that the timing of the falling edge of the clock signal changes from clock cycle to clock cycle. If the circuitry is optimized for operation under one clock signal duty cycle condition, then it typically is not optimized for operation under another clock signal duty cycle condition. A time margin is typically built into the circuitry so that the circuitry of the pseudo-dual port memory will operate correctly under all clock signal duty cycle conditions. This time margin translates into wasted time under certain operating conditions where the time margin is not required for proper operation. The maximum clock frequency of the pseudo-dual port memory is therefore specified to be lower than it could be were there no such time margin.
An improved pseudo-dual port memory is desired.